Phase-locked loop (PLL) circuits are used to generate clock signals having a fixed phase relationship with respect to a reference clock signal. Typical phase-locked loop circuits include a voltage-controlled oscillator (VCO), a loop filter, and a phase-frequency detector. The VCO generates a clock signal having a frequency that varies based on a control voltage, and the phase-frequency detector adjusts the control voltage via the loop filter based on a comparison of the phase relationship of the clock signal and the reference clock signal.
One type of VCO is a ring-oscillator VCO, in which an odd number of ring-oscillator stages are connected in series. Each stage inverts an input signal provided by a prior stage and passes the inverted input signal to a next ring-oscillator stage. The final ring-oscillator stage has an output signal that is provided as a clock signal and that is fed back to the input of the first ring-oscillator stage to form a loop. Due to alternating input voltages and gate delay, the clock signal from the ring-oscillator has a predictable frequency that is generally proportional to an input control voltage. In existing ring-oscillator VCO circuits, gain stages in each ring-oscillator stage function the same way, resulting in VCO circuits with limited tuning range and nonlinear frequency-control voltage relationships, which are undesirable features for a PLL circuit.